Silicon dioxide is the material which is most commonly etched in the fabrication of semiconductor devices. Typically, a layer of silicon dioxide is formed on a silicon substrate by the thermal oxidation of a prepared silicon wafer surface. The silicon dioxide surface is then coated with a photoresist which is imaged with a microstructure pattern. After photo-development, the patterned photoresist serves as a mask for etching the underlying silicon dioxide layer.
Conventional silicon dioxide etching techniques utilize hydrofluoric acid-based solutions into which the masked silicon dioxide is immersed. The exposed silicon dioxide is rapidly removed while the masked silicon dioxide is generally protected by the patterned photoresist coating. However, vertical and lateral etch penetration into the silicon dioxide is difficult to control using this conventional etching technique. As the hydrofluoric acid etchant dissolves the silicon dioxide surface, uncontrolled lateral etching occurs which produces irregular cuspate etching beneath the photoresist mask. Furthermore, the exposed silicon dioxide etches at a single rate, making it difficult to produce a silicon dioxide layer having several different thicknesses.
It is well known that by bombarding silicon dioxide with accelerated ions, the etch rate of the ion-bombarded oxide can be increased. In enhancing etching by ion bombardment, high-energy ions are directed toward a resist-masked silicon dioxide layer. The ions strike exposed areas of the silicon dioxide, causing ion-bombardment damage to the oxide, while the masked areas are protected from ion damage. The depth of the ion damage in the bombarded silicon dioxide is dependent upon the ion implant dose and energy. It is known that hydrofluoric acid-based etchants etch the ion-bombarded regions more rapidly than the unimplanted regions. However, the etch rate is too fast and the etch rate differential between implanted and unimplanted oxide is too small for accurate etch control. With prior conventional etchants, the differential in etch rate between implanted and unimplanted regions is typically a multiple between about 2 and 6. These prior conventional etchants thus still produce significant unwanted lateral etching of unimplanted sidewalls. They also would produce significant vertical overetching beyond the depth of the bombarded region, if the etching is not stopped quickly enough after the thickness of the ion-bombarded area is etched away.
The increasing criticality of semiconductor device geometry parameters on device electrical performance has generated a need for a high degree of control over the etching process. It is desirable that silicon dioxide be selectively etched with submicrometer precision. For example, it may be desired to fabricate MOS transistors having various gate characteristics or threshold voltages on a single chip by providing various silicon dioxide thicknesses in the gate areas of such transistors. It may also be desired to form sharp trenches in silicon dioxide layers to promote grapho-epitaxy or to simply form smaller transistor features, such as smaller contact windows. Accordingly, there is a need for a method of precisely controlling etch parameters during silicon dioxide microstructure fabrication.